diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-24 21:46:58 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-24 21:46:58 +0000 |
| commit | 09bc0298650c76db1a06e20ca84c1dcb34071600 (patch) | |
| tree | 6fb4e150957445020262c64bacf93e4a91b5705a /lib/Target/Mips/MipsRegisterInfo.td | |
| parent | 3946043a80a043b3cf43b34bf068feaadc46485b (diff) | |
| download | external_llvm-09bc0298650c76db1a06e20ca84c1dcb34071600.zip external_llvm-09bc0298650c76db1a06e20ca84c1dcb34071600.tar.gz external_llvm-09bc0298650c76db1a06e20ca84c1dcb34071600.tar.bz2 | |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 7957004..b024ecd 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -257,7 +257,7 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, // Reserved D15]> { - let SubRegClassList = [FGR32, FGR32]; + let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; let MethodProtos = [{ iterator allocation_order_end(const MachineFunction &MF) const; }]; |