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author | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:00:26 +0000 |
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committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:00:26 +0000 |
commit | 0bf3dfbef60e36827df9c7e12b62503f1e345cd0 (patch) | |
tree | 2d216dbfb7ecf59bc8c895297ca198d605f6f844 /lib/Target/Mips/MipsRegisterInfo.td | |
parent | b485de5d8c3fe0c62c0b07f63f64bd10f6803c17 (diff) | |
download | external_llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.zip external_llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.gz external_llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.bz2 |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 9f9cae7..d015bf5 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -1,15 +1,15 @@ -//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// +//===- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Declarations that describe the MIPS register file -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // We have banks of 32 registers each. class MipsReg<string n> : Register<n> { @@ -44,9 +44,9 @@ class AFPR<bits<5> num, string n, list<Register> subregs> let SubRegIndices = [sub_fpeven, sub_fpodd]; } -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Registers -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// let Namespace = "Mips" in { @@ -145,9 +145,9 @@ let Namespace = "Mips" in { def FCR31 : Register<"31">; } -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Register Classes -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// def CPURegs : RegisterClass<"Mips", [i32], 32, // Return Values and Arguments |