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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-21 23:48:37 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-21 23:48:37 +0000 |
commit | 1024f290d1c81dd23ec452455eff8589a4419032 (patch) | |
tree | 307c10de8dfe8e868c2a5516959aff2dbff41741 /lib/Target/Mips/MipsRegisterInfo.td | |
parent | a9adbf6df7116b08cef168d5b2315b82a95075c2 (diff) | |
download | external_llvm-1024f290d1c81dd23ec452455eff8589a4419032.zip external_llvm-1024f290d1c81dd23ec452455eff8589a4419032.tar.gz external_llvm-1024f290d1c81dd23ec452455eff8589a4419032.tar.bz2 |
Add MIPS accumulator and DSP control registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 4015add..ae4813e 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -245,13 +245,45 @@ let Namespace = "Mips" in { // Hardware register $29 def HWR29 : Register<"29">; def HWR29_64 : Register<"29">; + + // Accum registers + def LO0 : Register<"ac0"> { + let Aliases = [LO]; + } + def HI0 : Register<"hi0"> { + let Aliases = [HI]; + } + def LO1 : Register<"ac1">; + def HI1 : Register<"hi1">; + def LO2 : Register<"ac2">; + def HI2 : Register<"hi2">; + def LO3 : Register<"ac3">; + def HI3 : Register<"hi3">; + + let SubRegIndices = [sub_32] in { + def LO0_64 : RegisterWithSubRegs<"ac0", [LO0]> { + let Aliases = [LO64]; + } + def HI0_64 : RegisterWithSubRegs<"hi0", [HI0]> { + let Aliases = [HI64]; + } + def LO1_64 : RegisterWithSubRegs<"ac1", [LO1]>; + def HI1_64 : RegisterWithSubRegs<"hi1", [HI1]>; + def LO2_64 : RegisterWithSubRegs<"ac2", [LO2]>; + def HI2_64 : RegisterWithSubRegs<"hi2", [HI2]>; + def LO3_64 : RegisterWithSubRegs<"ac3", [LO3]>; + def HI3_64 : RegisterWithSubRegs<"hi3", [HI3]>; + } + + def DSPCtrl : Register<"dspctrl">; } //===----------------------------------------------------------------------===// // Register Classes //===----------------------------------------------------------------------===// -def CPURegs : RegisterClass<"Mips", [i32], 32, (add +class CPURegsClass<list<ValueType> regTypes> : + RegisterClass<"Mips", regTypes, 32, (add // Reserved ZERO, AT, // Return Values and Arguments @@ -265,6 +297,9 @@ def CPURegs : RegisterClass<"Mips", [i32], 32, (add // Reserved K0, K1, GP, SP, FP, RA)>; +def CPURegs : CPURegsClass<[i32]>; +def DSPRegs : CPURegsClass<[v4i8, v2i16]>; + def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add // Reserved ZERO_64, AT_64, @@ -322,3 +357,9 @@ def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; +// Accum Registers +def HIRegs : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; +def LORegs : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; + +def HI64Regs : RegisterClass<"Mips", [i64], 64, (sequence "HI%u_64", 0, 3)>; +def LO64Regs : RegisterClass<"Mips", [i64], 64, (sequence "LO%u_64", 0, 3)>; |