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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-04 03:30:34 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-04 03:30:34 +0000 |
| commit | 338607ae0ddab00e197222e769748e2e0c0b4e18 (patch) | |
| tree | ae0cdec113d5fb087b1bf0eccaecfdfae2432542 /lib/Target/Mips/MipsRegisterInfo.td | |
| parent | 7855ec62c3b6b5b7e6d3fada589511abd964fdb3 (diff) | |
| download | external_llvm-338607ae0ddab00e197222e769748e2e0c0b4e18.zip external_llvm-338607ae0ddab00e197222e769748e2e0c0b4e18.tar.gz external_llvm-338607ae0ddab00e197222e769748e2e0c0b4e18.tar.bz2 | |
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index ce399a0..f7cc1f6 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -263,9 +263,7 @@ def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add // Callee save S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, // Reserved - ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)> { - let SubRegClasses = [(CPURegs sub_32)]; -} + ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; // 64bit fp: // * FGR64 - 32 64-bit registers @@ -282,22 +280,16 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Not preserved across procedure calls D2, D3, D4, D5, D8, D9, // Callee save - D10, D11, D12, D13, D14, D15)> { - let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; -} + D10, D11, D12, D13, D14, D15)>; -def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> { - let SubRegClasses = [(FGR32 sub_32)]; -} +def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; // Condition Register for floating point operations def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>; // Hi/Lo Registers def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; -def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)> { - let SubRegClasses = [(HILO sub_32)]; -} +def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; // Hardware registers def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; |