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author | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-09 22:11:26 +0000 |
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committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-09 22:11:26 +0000 |
commit | 588158674572502daefbae5225715070274e6482 (patch) | |
tree | d7f5a70aa5faecbb6f9c48f5ce77b3c24de6710e /lib/Target/Mips/MipsRegisterInfo.td | |
parent | c3ab388ba9574eb93c44ed57ea46acd4f623b5dc (diff) | |
download | external_llvm-588158674572502daefbae5225715070274e6482.zip external_llvm-588158674572502daefbae5225715070274e6482.tar.gz external_llvm-588158674572502daefbae5225715070274e6482.tar.bz2 |
Make F31 and D15 non-reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index f0db518..9c288e4 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -182,9 +182,7 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Not preserved across procedure calls D2, D3, D4, D5, D8, D9, // Callee save - D10, D11, D12, D13, D14, - // Reserved - D15)> { + D10, D11, D12, D13, D14, D15)> { let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; } |