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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-16 22:19:56 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-16 22:19:56 +0000 |
| commit | 66e19c3e9db6e2727be21074a52f5c9fa187050f (patch) | |
| tree | c69324d29909da842676fa2e4b2c502c6f446625 /lib/Target/Mips/MipsRegisterInfo.td | |
| parent | bec5463937a4e0832188327e43cf00cb7e712e38 (diff) | |
| download | external_llvm-66e19c3e9db6e2727be21074a52f5c9fa187050f.zip external_llvm-66e19c3e9db6e2727be21074a52f5c9fa187050f.tar.gz external_llvm-66e19c3e9db6e2727be21074a52f5c9fa187050f.tar.bz2 | |
This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.
As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index f7cc1f6..8a13bd1 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -265,6 +265,13 @@ def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add // Reserved ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; +def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add + // Return Values and Arguments + V0, V1, A0, A1, A2, A3, + // Callee save + S0, S1)>; + + // 64bit fp: // * FGR64 - 32 64-bit registers // * AFGR64 - 16 32-bit even registers (32-bit FP Mode) |