diff options
| author | Reed Kotler <rkotler@mips.com> | 2012-09-28 02:26:24 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2012-09-28 02:26:24 +0000 |
| commit | c94a38ff1732b960a551c7c1a4c50ede5c4737b4 (patch) | |
| tree | 3438d181ef9da5244338e39b0640abc020328b46 /lib/Target/Mips/MipsRegisterInfo.td | |
| parent | 83ef63efced9a957fe370134314645d2188c7203 (diff) | |
| download | external_llvm-c94a38ff1732b960a551c7c1a4c50ede5c4737b4.zip external_llvm-c94a38ff1732b960a551c7c1a4c50ede5c4737b4.tar.gz external_llvm-c94a38ff1732b960a551c7c1a4c50ede5c4737b4.tar.bz2 | |
1. Add load/store words from the stack
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 3d99e0d..a72e3b8 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -302,6 +302,7 @@ def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; +def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>; // 64bit fp: // * FGR64 - 32 64-bit registers |