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author | Stephen Hines <srhines@google.com> | 2014-07-21 00:45:20 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2014-07-25 00:48:57 -0700 |
commit | cd81d94322a39503e4a3e87b6ee03d4fcb3465fb (patch) | |
tree | 81b7dd2bb4370a392f31d332a566c903b5744764 /lib/Target/Mips/MipsRegisterInfo.td | |
parent | 0c5f13c0c4499eaf42ab5e9e2ceabd4e20e36861 (diff) | |
download | external_llvm-cd81d94322a39503e4a3e87b6ee03d4fcb3465fb.zip external_llvm-cd81d94322a39503e4a3e87b6ee03d4fcb3465fb.tar.gz external_llvm-cd81d94322a39503e4a3e87b6ee03d4fcb3465fb.tar.bz2 |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 875a596..6323da3 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -340,6 +340,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; +// Used to reserve odd registers when given -mattr=+nooddspreg +def OddSP : RegisterClass<"Mips", [f32], 32, + (add (decimate (sequence "F%u", 1, 31), 2), + (decimate (sequence "F_HI%u", 1, 31), 2))>, + Unallocatable; + // FP control registers. def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, Unallocatable; @@ -348,6 +354,10 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, Unallocatable; +// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. +// This class allows us to represent this in codegen patterns. +def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; + def MSA128B: RegisterClass<"Mips", [v16i8], 128, (sequence "W%u", 0, 31)>; def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, @@ -512,6 +522,12 @@ def FGR32Opnd : RegisterOperand<FGR32> { let ParserMatchClass = FGR32AsmOperand; } +def FGRCCOpnd : RegisterOperand<FGRCC> { + // The assembler doesn't use register classes so we can re-use + // FGR32AsmOperand. + let ParserMatchClass = FGR32AsmOperand; +} + def FGRH32Opnd : RegisterOperand<FGRH32> { let ParserMatchClass = FGRH32AsmOperand; } |