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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-10 20:04:40 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-10 20:04:40 +0000 |
commit | e8068692f924a1577075bd2d7b72b44820e0ffb2 (patch) | |
tree | ab81235de26ab5725b86bb2fd8416ac62ca943c5 /lib/Target/Mips/MipsRegisterInfo.td | |
parent | 4daaed1c7077deb185628a86252afdbbbaf5d3db (diff) | |
download | external_llvm-e8068692f924a1577075bd2d7b72b44820e0ffb2.zip external_llvm-e8068692f924a1577075bd2d7b72b44820e0ffb2.tar.gz external_llvm-e8068692f924a1577075bd2d7b72b44820e0ffb2.tar.bz2 |
[mips] Set HWEncoding field of registers. Use delete function
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 49 |
1 files changed, 20 insertions, 29 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 391c19e..f07a10c 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -19,52 +19,43 @@ def sub_hi : SubRegIndex; } // We have banks of 32 registers each. -class MipsReg<string n> : Register<n> { - field bits<5> Num; +class MipsReg<bits<16> Enc, string n> : Register<n> { + let HWEncoding = Enc; let Namespace = "Mips"; } -class MipsRegWithSubRegs<string n, list<Register> subregs> +class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> { - field bits<5> Num; + let HWEncoding = Enc; let Namespace = "Mips"; } // Mips CPU Registers -class MipsGPRReg<bits<5> num, string n> : MipsReg<n> { - let Num = num; -} +class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; // Mips 64-bit CPU Registers -class Mips64GPRReg<bits<5> num, string n, list<Register> subregs> - : MipsRegWithSubRegs<n, subregs> { - let Num = num; +class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> + : MipsRegWithSubRegs<Enc, n, subregs> { let SubRegIndices = [sub_32]; } // Mips 32-bit FPU Registers -class FPR<bits<5> num, string n> : MipsReg<n> { - let Num = num; -} +class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; // Mips 64-bit (aliased) FPU Registers -class AFPR<bits<5> num, string n, list<Register> subregs> - : MipsRegWithSubRegs<n, subregs> { - let Num = num; +class AFPR<bits<16> Enc, string n, list<Register> subregs> + : MipsRegWithSubRegs<Enc, n, subregs> { let SubRegIndices = [sub_fpeven, sub_fpodd]; let CoveredBySubRegs = 1; } -class AFPR64<bits<5> num, string n, list<Register> subregs> - : MipsRegWithSubRegs<n, subregs> { - let Num = num; +class AFPR64<bits<16> Enc, string n, list<Register> subregs> + : MipsRegWithSubRegs<Enc, n, subregs> { let SubRegIndices = [sub_32]; } // Mips Hardware Registers -class HWR<bits<5> num, string n> : MipsReg<n> { - let Num = num; -} +class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; //===----------------------------------------------------------------------===// // Registers @@ -239,21 +230,21 @@ let Namespace = "Mips" in { def FCR31 : Register<"31">; // fcc0 register - def FCC0 : Register<"fcc0">; + def FCC0 : MipsReg<0, "fcc0">; // PC register def PC : Register<"pc">; // Hardware register $29 - def HWR29 : Register<"29">; - def HWR29_64 : Register<"29">; + def HWR29 : MipsReg<29, "29">; + def HWR29_64 : MipsReg<29, "29">; // Accum registers let SubRegIndices = [sub_lo, sub_hi] in - def AC0 : RegisterWithSubRegs<"ac0", [LO, HI]>; - def AC1 : Register<"ac1">; - def AC2 : Register<"ac2">; - def AC3 : Register<"ac3">; + def AC0 : MipsRegWithSubRegs<0, "ac0", [LO, HI]>; + def AC1 : MipsReg<1, "ac1">; + def AC2 : MipsReg<2, "ac2">; + def AC3 : MipsReg<3, "ac3">; def DSPCtrl : Register<"dspctrl">; } |