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author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-05 19:05:21 +0000 |
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committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-05 19:05:21 +0000 |
commit | 225ca9cdd70de3d12641b0aba7daf6cb568a7ebd (patch) | |
tree | 4e9448b1e96f4e7792d2dcb85781c53ddef8dd39 /lib/Target/Mips/MipsSubtarget.cpp | |
parent | 126d90770bdb17e6925b2fe26de99aa079b7b9b3 (diff) | |
download | external_llvm-225ca9cdd70de3d12641b0aba7daf6cb568a7ebd.zip external_llvm-225ca9cdd70de3d12641b0aba7daf6cb568a7ebd.tar.gz external_llvm-225ca9cdd70de3d12641b0aba7daf6cb568a7ebd.tar.bz2 |
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSubtarget.cpp')
-rw-r--r-- | lib/Target/Mips/MipsSubtarget.cpp | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 2bfb82a..31e777d 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -14,15 +14,29 @@ #include "MipsSubtarget.h" #include "Mips.h" #include "MipsGenSubtarget.inc" +#include "llvm/Module.h" using namespace llvm; MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M, const std::string &FS, bool little) : - IsMipsIII(false), - IsLittle(little) + MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false), + IsFP64bit(false), IsGP64bit(false), HasAllegrexVFPU(false), IsAllegrex(false) { std::string CPU = "mips1"; // Parse features string. ParseSubtargetFeatures(FS, CPU); + + // When only the target triple is specified and is + // a allegrex target, set the features. We also match + // big and little endian allegrex cores (dont really + // know if a big one exists) + const std::string& TT = M.getTargetTriple(); + if (TT.find("mipsallegrex") != std::string::npos) { + MipsABI = EABI; + IsSingleFloat = true; + MipsArchVersion = Mips2; + HasAllegrexVFPU = true; // Enables Allegrex Vector FPU (not supported yet) + IsAllegrex = true; + } } |