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authorLogan Chien <loganchien@google.com>2011-12-16 09:08:45 +0800
committerLogan Chien <loganchien@google.com>2011-12-16 13:28:58 +0800
commita1e6e241a813f81be2d2f36ab60c950ca297574b (patch)
treecf2d7ec5c63f40e2b66d8be7737496719a0d7902 /lib/Target/Mips/MipsTargetMachine.h
parentac212abcc6d858470ad35ce7d660af0c1800364a (diff)
parentddecfe54a35ffbe0675f7f33e493734fd60b2495 (diff)
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Merge with LLVM upstream r146714 (Dec 16th 2011)
Change-Id: Ied458adb08bf9a69250cbcee9b14b44d17e8701a
Diffstat (limited to 'lib/Target/Mips/MipsTargetMachine.h')
-rw-r--r--lib/Target/Mips/MipsTargetMachine.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
index e40d9e2..6842373 100644
--- a/lib/Target/Mips/MipsTargetMachine.h
+++ b/lib/Target/Mips/MipsTargetMachine.h
@@ -38,7 +38,7 @@ namespace llvm {
public:
MipsTargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle);
@@ -82,7 +82,7 @@ namespace llvm {
class MipsebTargetMachine : public MipsTargetMachine {
public:
MipsebTargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};
@@ -92,7 +92,7 @@ public:
class MipselTargetMachine : public MipsTargetMachine {
public:
MipselTargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};
@@ -103,6 +103,7 @@ class Mips64ebTargetMachine : public MipsTargetMachine {
public:
Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};
@@ -113,6 +114,7 @@ class Mips64elTargetMachine : public MipsTargetMachine {
public:
Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};