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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-04-11 22:59:08 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-04-11 22:59:08 +0000 |
| commit | 1cc6333161be8bbeb516bc7c74d4400dca58b997 (patch) | |
| tree | 10311c6783788ad8f5e1e8492ce3aea57d083b40 /lib/Target/Mips | |
| parent | c12a6e6b53bb6df62a0020bda91206fd149c430a (diff) | |
| download | external_llvm-1cc6333161be8bbeb516bc7c74d4400dca58b997.zip external_llvm-1cc6333161be8bbeb516bc7c74d4400dca58b997.tar.gz external_llvm-1cc6333161be8bbeb516bc7c74d4400dca58b997.tar.bz2 | |
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
otherwise expand FNEG during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 7 |
2 files changed, 9 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 842988c..6a23bc3 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -216,6 +216,11 @@ MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FREM, MVT::f32, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand); + if (!TM.Options.NoNaNsFPMath) { + setOperationAction(ISD::FNEG, MVT::f32, Expand); + setOperationAction(ISD::FNEG, MVT::f64, Expand); + } + setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 332bc11..b655945 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -190,9 +190,10 @@ let Predicates = [IsFP64bit] in { def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>; } -let Predicates = [NoNaNsFPMath] in -defm FABS : FFR1P_M<0x5, "abs", fabs>; -defm FNEG : FFR1P_M<0x7, "neg", fneg>; +let Predicates = [NoNaNsFPMath] in { + defm FABS : FFR1P_M<0x5, "abs", fabs>; + defm FNEG : FFR1P_M<0x7, "neg", fneg>; +} defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>; // The odd-numbered registers are only referenced when doing loads, |