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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-21 17:13:47 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-21 17:13:47 +0000 |
| commit | 1d4d32398ddb19520b2a84acae3b7807ad74602b (patch) | |
| tree | 2171fef203b9498a3c8abb5c745005f7db14fcb8 /lib/Target/Mips | |
| parent | b9c26dcb2438266567ce94570bf294d00d10cc87 (diff) | |
| download | external_llvm-1d4d32398ddb19520b2a84acae3b7807ad74602b.zip external_llvm-1d4d32398ddb19520b2a84acae3b7807ad74602b.tar.gz external_llvm-1d4d32398ddb19520b2a84acae3b7807ad74602b.tar.bz2 | |
[mips] Add instruction selection patterns for blez and bgez.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 391b23e..df717fe 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -294,6 +294,11 @@ def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, ZERO_64>; +def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), + (BLEZ64 i64:$lhs, bb:$dst)>; +def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), + (BGEZ64 i64:$lhs, bb:$dst)>; + // setcc patterns defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; defm : SetlePats<CPU64Regs, SLT64, SLTu64>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index f37a93e..3febc81 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1277,6 +1277,11 @@ def : MipsPat<(brcond RC:$cond, bb:$dst), defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; +def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), + (BLEZ i32:$lhs, bb:$dst)>; +def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), + (BGEZ i32:$lhs, bb:$dst)>; + // setcc patterns multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, Instruction SLTuOp, Register ZEROReg> { |