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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-01-04 19:38:05 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-01-04 19:38:05 +0000 |
| commit | 1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b (patch) | |
| tree | ad03d81bd72506a129146e0a9d095a7e28f4a30a /lib/Target/Mips | |
| parent | 50c30427405142f1b587edee846606184ae6af8e (diff) | |
| download | external_llvm-1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b.zip external_llvm-1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b.tar.gz external_llvm-1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b.tar.bz2 | |
[mips] 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.h | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips16RegisterInfo.h | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 12 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 2 |
4 files changed, 14 insertions, 8 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h index 16487e7..3704e25 100644 --- a/lib/Target/Mips/Mips16InstrInfo.h +++ b/lib/Target/Mips/Mips16InstrInfo.h @@ -96,8 +96,9 @@ private: unsigned Reg1, unsigned Reg2) const; // Adjust SP by Amount bytes where bytes can be up to 32bit number. - void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const; + void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; }; diff --git a/lib/Target/Mips/Mips16RegisterInfo.h b/lib/Target/Mips/Mips16RegisterInfo.h index ba0d25d..6101739 100644 --- a/lib/Target/Mips/Mips16RegisterInfo.h +++ b/lib/Target/Mips/Mips16RegisterInfo.h @@ -22,7 +22,8 @@ class Mips16InstrInfo; class Mips16RegisterInfo : public MipsRegisterInfo { const Mips16InstrInfo &TII; public: - Mips16RegisterInfo(const MipsSubtarget &Subtarget, const Mips16InstrInfo &TII); + Mips16RegisterInfo(const MipsSubtarget &Subtarget, + const Mips16InstrInfo &TII); void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 3961dd6..d1f4458 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -330,8 +330,12 @@ def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; -def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; -def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; -def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; -def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"dmfc0 $rt, $rd", + (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"dmtc0 $rt, $rd", + (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"dmfc2 $rt, $rd", + (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"dmtc2 $rt, $rd", + (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index b9f24b8..c026b5d 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -173,7 +173,7 @@ class FJ<bits<6> op> let Inst{25-0} = target; } - //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> //===----------------------------------------------------------------------===// class MFC3OP_FM<bits<6> op, bits<5> mfmt> |