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| author | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:16 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:16 +0000 |
| commit | 3ccbd47ecb83ad758ff310dea8c4f54d53f39326 (patch) | |
| tree | 306e875385a2899f87687c1f3a9c6ce65893764a /lib/Target/Mips | |
| parent | f09769067fa01d45ddb794aa4af906f6ec2b085e (diff) | |
| download | external_llvm-3ccbd47ecb83ad758ff310dea8c4f54d53f39326.zip external_llvm-3ccbd47ecb83ad758ff310dea8c4f54d53f39326.tar.gz external_llvm-3ccbd47ecb83ad758ff310dea8c4f54d53f39326.tar.bz2 | |
When using inline asm constraints representing
non-floating point general registers allow 8 and 16-bit
elements.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index fc03ac5..bb36d76 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -3054,7 +3054,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'd': // Address register. Same as 'r' unless generating MIPS16 code. case 'y': // Same as 'r'. Exists for compatibility. case 'r': - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) return std::make_pair(0U, &Mips::CPURegsRegClass); assert(VT == MVT::i64 && "Unexpected type."); return std::make_pair(0U, &Mips::CPU64RegsRegClass); |