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author | Jack Carter <jcarter@mips.com> | 2012-08-28 19:07:39 +0000 |
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committer | Jack Carter <jcarter@mips.com> | 2012-08-28 19:07:39 +0000 |
commit | 69dba7e20476ec0e64791e47b498ae3a69619f7d (patch) | |
tree | 0db6a376d87abeb78ac6345e53868e7178a67746 /lib/Target/Mips | |
parent | c6c2ced38411215e5bf46ded787c23810160dfa7 (diff) | |
download | external_llvm-69dba7e20476ec0e64791e47b498ae3a69619f7d.zip external_llvm-69dba7e20476ec0e64791e47b498ae3a69619f7d.tar.gz external_llvm-69dba7e20476ec0e64791e47b498ae3a69619f7d.tar.bz2 |
Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into
dsll32 if the shift value is greater than 32.
For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r-- | lib/Target/Mips/MipsAsmPrinter.cpp | 44 |
1 files changed, 24 insertions, 20 deletions
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 00ff754..3b1509d 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -58,33 +58,37 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } - // Direct object specific instruction lowering - if (!OutStreamer.hasRawTextSupport()) - switch (MI->getOpcode()) { - case Mips::DSLL: - case Mips::DSRL: - case Mips::DSRA: - assert(MI->getNumOperands() == 3 && - "Invalid no. of machine operands for shift!"); - assert(MI->getOperand(2).isImm()); - int64_t Shift = MI->getOperand(2).getImm(); - if (Shift > 31) { - MCInst TmpInst0; - MCInstLowering.LowerLargeShift(MI, TmpInst0, Shift - 32); - OutStreamer.EmitInstruction(TmpInst0); - return; - } - break; - } - MachineBasicBlock::const_instr_iterator I = MI; MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); do { MCInst TmpInst0; + + // Direct object specific instruction lowering + if (!OutStreamer.hasRawTextSupport()) + switch (I->getOpcode()) { + // If shift amount is >= 32 it the inst needs to be lowered further + case Mips::DSLL: + case Mips::DSRL: + case Mips::DSRA: + { + assert(I->getNumOperands() == 3 && + "Invalid no. of machine operands for shift!"); + assert(I->getOperand(2).isImm()); + int64_t Shift = I->getOperand(2).getImm(); + if (Shift > 31) { + MCInst TmpInst0; + MCInstLowering.LowerLargeShift(I, TmpInst0, Shift - 32); + OutStreamer.EmitInstruction(TmpInst0); + return; + } + } + } + MCInstLowering.Lower(I++, TmpInst0); OutStreamer.EmitInstruction(TmpInst0); - } while ((I != E) && I->isInsideBundle()); + + } while ((I != E) && I->isInsideBundle()); // Delay slot check } //===----------------------------------------------------------------------===// |