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authorAkira Hatanaka <ahatanaka@mips.com>2013-08-28 00:34:17 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-08-28 00:34:17 +0000
commit6d55dfaf9124c3e5e54190090478d2f6384a51d4 (patch)
tree547a03615c32dbbc350532e42959f5d6394f0129 /lib/Target/Mips
parentc3e9457f6d66d1cc16fc37e39ed5fe13f835875c (diff)
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[mips] Set isAllocatable and CoveredBySubRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189430 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r--lib/Target/Mips/MipsRegisterInfo.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 022a9c0..22c4890 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -60,6 +60,7 @@ class AFPR<bits<16> Enc, string n, list<Register> subregs>
class AFPR64<bits<16> Enc, string n, list<Register> subregs>
: MipsRegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_lo, sub_hi];
+ let CoveredBySubRegs = 1;
}
// Mips 128-bit (aliased) MSA Registers
@@ -294,7 +295,8 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
// * FGR32 - 32 32-bit registers (single float only mode)
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
-def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>;
+def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
+ Unallocatable;
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments