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authorEric Christopher <echristo@apple.com>2012-05-07 06:25:19 +0000
committerEric Christopher <echristo@apple.com>2012-05-07 06:25:19 +0000
commitaf97f73ca03d16ffa069af65a494d0933665ce11 (patch)
tree03e8f785c09a7f189cb901be9cfda8d44acc403b /lib/Target/Mips
parent4adbefebd2eeeab4d7007b697b4cc20e40ba06b8 (diff)
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Add support for the 'x' constraint.
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156295 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index ca0472b..337a5e3 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -3001,7 +3001,8 @@ getConstraintType(const std::string &Constraint) const
// backwards compatibility.
// 'c' : A register suitable for use in an indirect
// jump. This will always be $25 for -mabicalls.
- // 'l' : The lo register.
+ // 'l' : The lo register. 1 word storage.
+ // 'x' : The hilo register pair. Double word storage.
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;
@@ -3010,6 +3011,7 @@ getConstraintType(const std::string &Constraint) const
case 'f':
case 'c':
case 'l':
+ case 'x':
return C_RegisterClass;
}
}
@@ -3045,6 +3047,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
break;
case 'c': // $25 for indirect jumps
case 'l': // lo register
+ case 'x': // hilo register pair
if (type->isIntegerTy())
weight = CW_SpecificReg;
break;
@@ -3097,6 +3100,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
if (VT == MVT::i32)
return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
+ case 'x': // register suitable for indirect jump
+ // Fixme: Not triggering the use of both hi and low
+ // This will generate an error message
+ return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
}
}
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);