diff options
| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-11-10 02:13:22 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-11-10 02:13:22 +0000 |
| commit | c4bb67c8d951feaa4a1429ea2ff0171a30d7d471 (patch) | |
| tree | bf3e77041a3c06f5473a2ba51a5d2d9ad6ee9ed4 /lib/Target/Mips | |
| parent | 201ab3acff18c0470950d43495419185e8a7afd3 (diff) | |
| download | external_llvm-c4bb67c8d951feaa4a1429ea2ff0171a30d7d471.zip external_llvm-c4bb67c8d951feaa4a1429ea2ff0171a30d7d471.tar.gz external_llvm-c4bb67c8d951feaa4a1429ea2ff0171a30d7d471.tar.bz2 | |
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/Mips.td | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 17 |
2 files changed, 12 insertions, 8 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 9c0e624..3e6437b 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -59,7 +59,8 @@ def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", "Mips2 ISA Support">; def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", - "Mips32 ISA Support", [FeatureCondMov]>; + "Mips32 ISA Support", + [FeatureCondMov, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", [FeatureMips32, FeatureSEInReg]>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 47f4dca..61f51e7 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -281,10 +281,13 @@ class EffectiveAddress<string instr_asm> : instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>; // Count Leading Ones/Zeros in Word -class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>: +class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>: FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src), - !strconcat(instr_asm, "\t$dst, $src"), - [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>; + !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>, + Requires<[HasBitCount]> { + let shamt = 0; + let rt = rd; +} // Sign Extend in Register. class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>: @@ -446,10 +449,10 @@ let Predicates = [HasSEInReg] in { } /// Count Leading -let Predicates = [HasBitCount] in { - let rt = 0 in - def CLZ : CountLeading<0b010110, "clz", ctlz>; -} +def CLZ : CountLeading<0b100000, "clz", + [(set CPURegs:$dst, (ctlz CPURegs:$src))]>; +def CLO : CountLeading<0b100001, "clo", + [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>; /// Byte Swap let Predicates = [HasSwap] in { |