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author | Matheus Almeida <matheus.almeida@imgtec.com> | 2013-10-21 11:47:56 +0000 |
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committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2013-10-21 11:47:56 +0000 |
commit | f89f66e61b26974bb73b5832d5825091873b51dc (patch) | |
tree | 780817da9685883ffa66c52a6630622a09e64797 /lib/Target/Mips | |
parent | 6701bb7283747b00bc814b1db784fdbbe03644a1 (diff) | |
download | external_llvm-f89f66e61b26974bb73b5832d5825091873b51dc.zip external_llvm-f89f66e61b26974bb73b5832d5825091873b51dc.tar.gz external_llvm-f89f66e61b26974bb73b5832d5825091873b51dc.tar.bz2 |
[mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to
slide left the source array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r-- | lib/Target/Mips/MipsMSAInstrFormats.td | 13 | ||||
-rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 31 |
2 files changed, 36 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 9a3a8cd..c9b3745 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -132,6 +132,19 @@ class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { + bits<5> rt; + bits<5> ws; + bits<5> wd; + + let Inst{25-23} = major; + let Inst{22-21} = df; + let Inst{20-16} = rt; + let Inst{15-11} = ws; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst { let Inst{25-16} = major; let Inst{5-0} = minor; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 992340d..f72aaae 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -912,10 +912,10 @@ class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; -class SLD_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010100>; -class SLD_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010100>; -class SLD_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010100>; -class SLD_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010100>; +class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; +class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; +class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; +class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; @@ -1222,6 +1222,17 @@ class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, InstrItinClass Itinerary = itin; } +class MSA_3R_INDEX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, + RegisterOperand ROWD, RegisterOperand ROWS, + RegisterOperand RORT, + InstrItinClass itin = NoItinerary> { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, RORT:$rt); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); + list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, RORT:$rt))]; + InstrItinClass Itinerary = itin; +} + class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, RegisterOperand ROWD, RegisterOperand ROWS = ROWD, RegisterOperand ROWT = ROWD, @@ -2246,10 +2257,14 @@ class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; -class SLD_B_DESC : MSA_3R_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; -class SLD_H_DESC : MSA_3R_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; -class SLD_W_DESC : MSA_3R_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; -class SLD_D_DESC : MSA_3R_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; +class SLD_B_DESC : MSA_3R_INDEX_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd, + MSA128BOpnd, GPR32Opnd>; +class SLD_H_DESC : MSA_3R_INDEX_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd, + MSA128HOpnd, GPR32Opnd>; +class SLD_W_DESC : MSA_3R_INDEX_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd, + MSA128WOpnd, GPR32Opnd>; +class SLD_D_DESC : MSA_3R_INDEX_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd, + MSA128DOpnd, GPR32Opnd>; class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>; class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>; |