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author | Justin Holewinski <jholewinski@nvidia.com> | 2013-05-31 12:14:49 +0000 |
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committer | Justin Holewinski <jholewinski@nvidia.com> | 2013-05-31 12:14:49 +0000 |
commit | 5443e7d79044f3198f2da044f1b389b40d9bea6f (patch) | |
tree | 2af410aedc2eb4f9a78443029eb71da208562589 /lib/Target/NVPTX/NVPTXTargetMachine.cpp | |
parent | 7ae921dbec5db9823c89fa736b2a4c3afe163e4f (diff) | |
download | external_llvm-5443e7d79044f3198f2da044f1b389b40d9bea6f.zip external_llvm-5443e7d79044f3198f2da044f1b389b40d9bea6f.tar.gz external_llvm-5443e7d79044f3198f2da044f1b389b40d9bea6f.tar.bz2 |
[NVPTX] Re-enable support for virtual registers in the final output
Now that 3.3 is branched, we are re-enabling virtual registers to help
iron out bugs before the next release. Some of the post-RA passes do
not play well with virtual registers, so we disable them for now. The
needed functionality of the PrologEpilogInserter pass is copied to a
new backend-specific NVPTXPrologEpilog pass.
The test for this commit is not breaking the existing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/NVPTX/NVPTXTargetMachine.cpp')
-rw-r--r-- | lib/Target/NVPTX/NVPTXTargetMachine.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 5b8ea1e..68f9bf7 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -107,6 +107,10 @@ public: virtual void addIRPasses(); virtual bool addInstSelector(); virtual bool addPreRegAlloc(); + virtual bool addPostRegAlloc(); + + virtual void addFastRegAlloc(FunctionPass *RegAllocPass); + virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); }; } // end anonymous namespace @@ -116,6 +120,15 @@ TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) { } void NVPTXPassConfig::addIRPasses() { + // The following passes are known to not play well with virtual regs hanging + // around after register allocation (which in our case, is *all* registers). + // We explicitly disable them here. We do, however, need some functionality + // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the + // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp). + disablePass(&PrologEpilogCodeInserterID); + disablePass(&MachineCopyPropagationID); + disablePass(&BranchFolderPassID); + TargetPassConfig::addIRPasses(); addPass(createGenericToNVVMPass()); } @@ -129,3 +142,17 @@ bool NVPTXPassConfig::addInstSelector() { } bool NVPTXPassConfig::addPreRegAlloc() { return false; } +bool NVPTXPassConfig::addPostRegAlloc() { + addPass(createNVPTXPrologEpilogPass()); + return false; +} + +void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { + // No reg alloc + addPass(&StrongPHIEliminationID); +} + +void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { + // No reg alloc + addPass(&StrongPHIEliminationID); +} |