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authorSanjiv Gupta <sanjiv.gupta@microchip.com>2008-05-14 11:31:39 +0000
committerSanjiv Gupta <sanjiv.gupta@microchip.com>2008-05-14 11:31:39 +0000
commit1f7b12b0e5ff11eb6601c65e00b454ad8a084559 (patch)
treebf88751f0f674e8c9193faf44ae20931d5d53448 /lib/Target/PIC16/PIC16ISelLowering.h
parent393ad0f5d2f3d0091d49be0822e432ef19323ba2 (diff)
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Detabification. Fixed indentation and spacing.
Changed cout to DOUT, and TODOs to FIXMEs. Other changes as per coding conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PIC16/PIC16ISelLowering.h')
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h
index a94ec4a..41650ee 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.h
+++ b/lib/Target/PIC16/PIC16ISelLowering.h
@@ -15,10 +15,10 @@
#ifndef PIC16ISELLOWERING_H
#define PIC16ISELLOWERING_H
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
#include "PIC16.h"
#include "PIC16Subtarget.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetLowering.h"
namespace llvm {
namespace PIC16ISD {
@@ -35,15 +35,15 @@ namespace llvm {
// Get the Lower 16 bits from a 32-bit immediate
Lo,
- Cmp, // PIC16 Generic Comparison instruction.
- Branch, // PIC16 Generic Branch Instruction.
- BTFSS, // PIC16 BitTest Instruction (Skip if set).
- BTFSC, // PIC16 BitTest Instruction (Skip if clear).
+ Cmp, // PIC16 Generic Comparison instruction.
+ Branch, // PIC16 Generic Branch Instruction.
+ BTFSS, // PIC16 BitTest Instruction (Skip if set).
+ BTFSC, // PIC16 BitTest Instruction (Skip if clear).
// PIC16 comparison to be converted to either XOR or SUB
// Following instructions cater to those convertions.
- XORCC,
- SUBCC,
+ XORCC,
+ SUBCC,
// Get the Global Address wrapped into a wrapper that also captures
// the bank or page.
@@ -73,9 +73,9 @@ namespace llvm {
SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG);
SDOperand RemoveHiLo(SDNode *, SelectionDAG &DAG,
- DAGCombinerInfo &DCI) const;
+ DAGCombinerInfo &DCI) const;
SDOperand LowerADDSUB(SDNode *, SelectionDAG &DAG,
- DAGCombinerInfo &DCI) const;
+ DAGCombinerInfo &DCI) const;
SDOperand LowerLOAD(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const;