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authorSanjiv Gupta <sanjiv.gupta@microchip.com>2009-06-03 15:31:12 +0000
committerSanjiv Gupta <sanjiv.gupta@microchip.com>2009-06-03 15:31:12 +0000
commit892c8caa3c5f4e177b9ef489d69af553d8b2e421 (patch)
tree1c76d6d044448c6ee024070c29bc988231770f8e /lib/Target/PIC16/PIC16InstrInfo.cpp
parent030019f113114184266910625b9074c4f1e1d97c (diff)
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FrameIndex could be used as a value (addressof (arg)) or as an address.
Expand it exactly like GlobalAddress. Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72776 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PIC16/PIC16InstrInfo.cpp')
-rw-r--r--lib/Target/PIC16/PIC16InstrInfo.cpp28
1 files changed, 28 insertions, 0 deletions
diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp
index 2a769e8..8418423 100644
--- a/lib/Target/PIC16/PIC16InstrInfo.cpp
+++ b/lib/Target/PIC16/PIC16InstrInfo.cpp
@@ -184,3 +184,31 @@ bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
return false;
}
+/// InsertBranch - Insert a branch into the end of the specified
+/// MachineBasicBlock. This operands to this method are the same as those
+/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
+/// returns success and when an unconditional branch (TBB is non-null, FBB is
+/// null, Cond is empty) needs to be inserted. It returns the number of
+/// instructions inserted.
+unsigned PIC16InstrInfo::
+InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ const SmallVectorImpl<MachineOperand> &Cond) const {
+ // Shouldn't be a fall through.
+ assert(TBB && "InsertBranch must not be told to insert a fallthrough");
+
+ if (FBB == 0) { // One way branch.
+ if (Cond.empty()) {
+ // Unconditional branch?
+ DebugLoc dl = DebugLoc::getUnknownLoc();
+ BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
+ }
+ return 1;
+ }
+
+ // FIXME: If the there are some conditions specified then conditional branch
+ // should be generated.
+ // For the time being no instruction is being generated therefore
+ // returning NULL.
+ return 0;
+}