Adding files for Microchip's PIC16 target.

A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the 
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory 
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory. 

It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register). 

Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51027 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 84 insertions, 0 deletions

diff --git a/lib/Target/PIC16/PIC16RegisterInfo.td b/lib/Target/PIC16/PIC16RegisterInfo.td
new file mode 100644
index 0000000..21cc3e5
--- /dev/null
+++ b/lib/Target/PIC16/PIC16RegisterInfo.td
@@ -0,0 +1,84 @@
+//===- PIC16RegisterInfo.td - PIC16 Register defs ------------*- tblgen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source 
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the PIC16 register file
+//===----------------------------------------------------------------------===//
+
+// We have banks of 32 registers each.
+class PIC16Reg<string n> : Register<n> {
+  field bits<5> Num;
+  let Namespace = "PIC16";
+}
+
+// PIC16 CPU Registers
+class PIC16GPRReg<bits<5> num, string n> : PIC16Reg<n> {
+  let Num = num;
+}
+
+// CPU GPR Registers
+def FSR0 : PIC16GPRReg< 0, "FSR0">, DwarfRegNum<[0]>;
+def FSR1 : PIC16GPRReg< 1, "FSR1">, DwarfRegNum<[1]>;
+
+// CPU Registers Class
+def PTRRegs : RegisterClass<"PIC16", [i16], 8, 
+  [FSR0, FSR1]>
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    PTRRegsClass::iterator
+    PTRRegsClass::allocation_order_end(const MachineFunction &MF) const {
+      return end();
+    }
+  }];
+}
+
+def WREG : PIC16GPRReg< 0, "WREG">, DwarfRegNum<[0]>;
+
+// CPU Registers Class
+def CPURegs : RegisterClass<"PIC16", [i8], 8, 
+  [WREG]>
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    CPURegsClass::iterator
+    CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
+      return end();
+    }
+  }];
+}
+
+def STATUSREG : PIC16GPRReg<2, "STATUS">, DwarfRegNum<[0]>;
+
+// STATUS Registers Class
+def STATUSRegs : RegisterClass<"PIC16", [i8], 8, 
+  [STATUSREG]>;
+
+
+// Dummy stack pointer.
+def STKPTR : PIC16GPRReg< 0, "SP">, DwarfRegNum<[0]>;
+
+// CPU Registers Class
+def STKRegs : RegisterClass<"PIC16", [i8], 8, 
+  [STKPTR]>
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    STKRegsClass::iterator
+    STKRegsClass::allocation_order_end(const MachineFunction &MF) const {
+      return end();
+    }
+  }];
+}