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| author | Daniel Dunbar <daniel@zuster.org> | 2012-02-28 15:36:07 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2012-02-28 15:36:07 +0000 |
| commit | 20bd5296cec8d8d597ab9db2aca7346a88e580c8 (patch) | |
| tree | 5ef20ff8f6ec87dd9f39553b8e0f8ad0463280e2 /lib/Target/PTX | |
| parent | ed1242184cabdd3357f035da9ad30ba4c08ff50a (diff) | |
| download | external_llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.zip external_llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.gz external_llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.bz2 | |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PTX')
| -rw-r--r-- | lib/Target/PTX/PTXISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PTX/PTXISelLowering.h | 5 |
2 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/PTX/PTXISelLowering.cpp b/lib/Target/PTX/PTXISelLowering.cpp index e5d4edc..321b658 100644 --- a/lib/Target/PTX/PTXISelLowering.cpp +++ b/lib/Target/PTX/PTXISelLowering.cpp @@ -373,7 +373,7 @@ SDValue PTXTargetLowering:: SDValue PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool doesNotRet, bool &isTailCall, + bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/PTX/PTXISelLowering.h b/lib/Target/PTX/PTXISelLowering.h index fd20982..38f8caa 100644 --- a/lib/Target/PTX/PTXISelLowering.h +++ b/lib/Target/PTX/PTXISelLowering.h @@ -64,8 +64,9 @@ class PTXTargetLowering : public TargetLowering { SelectionDAG &DAG) const; virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, - bool isVarArg, bool doesNotRet, bool &isTailCall, + LowerCall(SDValue Chain, SDValue Callee, + CallingConv::ID CallConv, bool isVarArg, + bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, |