Add simple arithmetics and %type directive for PTX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119485 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 51 insertions, 9 deletions

diff --git a/lib/Target/PTX/PTXAsmPrinter.cpp b/lib/Target/PTX/PTXAsmPrinter.cpp
index b861807..175b3c4 100644
--- a/lib/Target/PTX/PTXAsmPrinter.cpp
+++ b/lib/Target/PTX/PTXAsmPrinter.cpp
@@ -64,14 +64,26 @@ static const char PARAM_PREFIX[] = "__param_";
 static const char *getRegisterTypeName(unsigned RegNo){
 #define TEST_REGCLS(cls, clsstr) \
   if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
-  TEST_REGCLS(RRegs32, .s32);
-  TEST_REGCLS(Preds, .pred);
+  TEST_REGCLS(RRegs32, s32);
+  TEST_REGCLS(Preds, pred);
 #undef TEST_REGCLS
 
   llvm_unreachable("Not in any register class!");
   return NULL;
 }
 
+static const char *getInstructionTypeName(const MachineInstr *MI)
+{
+  for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO = MI->getOperand(i);
+    if (MO.getType() == MachineOperand::MO_Register)
+      return getRegisterTypeName(MO.getReg());
+  }
+
+  llvm_unreachable("No reg operand found in instruction!");
+  return NULL;
+}
+
 bool PTXAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   SetupMachineFunction(MF);
   EmitFunctionDeclaration();
@@ -89,7 +101,7 @@ void PTXAsmPrinter::EmitFunctionBodyStart() {
        i = MFI->localVarRegBegin(), e = MFI->localVarRegEnd(); i != e; ++ i) {
     unsigned reg = *i;
 
-    std::string def = "\t.reg ";
+    std::string def = "\t.reg .";
     def += getRegisterTypeName(reg);
     def += ' ';
     def += getRegisterName(reg);
@@ -99,11 +111,21 @@ void PTXAsmPrinter::EmitFunctionBodyStart() {
 }
 
 void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) {
-  SmallString<128> str;
-  raw_svector_ostream OS(str);
+  SmallString<128> sstr;
+  raw_svector_ostream OS(sstr);
   printInstruction(MI, OS);
   OS << ';';
-  OutStreamer.EmitRawText(OS.str());
+
+  // Replace "%type" if found
+  StringRef strref = OS.str();
+  size_t pos;
+  if ((pos = strref.find("%type")) == StringRef::npos) {
+    OutStreamer.EmitRawText(strref);
+    return;
+  }
+  std::string str = strref;
+  str.replace(pos, /*strlen("%type")==*/5, getInstructionTypeName(MI));
+  OutStreamer.EmitRawText(StringRef(str));
 }
 
 void PTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
@@ -141,7 +163,7 @@ void PTXAsmPrinter::EmitFunctionDeclaration() {
   // Print return register
   reg = MFI->retReg();
   if (!isKernel && reg != PTX::NoRegister) {
-    decl += " (.reg "; // FIXME: could it return in .param space?
+    decl += " (.reg ."; // FIXME: could it return in .param space?
     decl += getRegisterTypeName(reg);
     decl += " ";
     decl += getRegisterName(reg);
@@ -170,7 +192,7 @@ void PTXAsmPrinter::EmitFunctionDeclaration() {
         assert(reg != PTX::NoRegister && "Not a valid register!");
         if (i != b)
           decl += ", ";
-        decl += ".reg ";
+        decl += ".reg .";
         decl += getRegisterTypeName(reg);
         decl += " ";
         decl += getRegisterName(reg);
diff --git a/lib/Target/PTX/PTXInstrInfo.td b/lib/Target/PTX/PTXInstrInfo.td
index e5dd334..71d9016 100644
--- a/lib/Target/PTX/PTXInstrInfo.td
+++ b/lib/Target/PTX/PTXInstrInfo.td
@@ -27,9 +27,29 @@ def PTXret
   : SDNode<"PTXISD::RET",  SDTNone, [SDNPHasChain]>;
 
 //===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+multiclass INT3<string opcstr, SDNode opnode> {
+  def rr : InstPTX<(outs RRegs32:$d),
+                   (ins RRegs32:$a, RRegs32:$b),
+                   !strconcat(opcstr, ".%type\t$d, $a, $b"),
+                   [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
+  def ri : InstPTX<(outs RRegs32:$d),
+                   (ins RRegs32:$a, i32imm:$b),
+                   !strconcat(opcstr, ".%type\t$d, $a, $b"),
+                   [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
+}
+
+//===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
+///===- Integer Arithmetic Instructions -----------------------------------===//
+
+defm ADD : INT3<"add", add>;
+defm SUB : INT3<"sub", sub>;
+
 ///===- Data Movement and Conversion Instructions -------------------------===//
 
 let neverHasSideEffects = 1 in {
@@ -37,7 +57,7 @@ let neverHasSideEffects = 1 in {
   def MOVpp
     : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
   def MOVrr
-    : InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.s32\t$d, $a", []>;
+    : InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {