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authorChe-Liang Chiou <clchiou@gmail.com>2010-12-06 04:00:03 +0000
committerChe-Liang Chiou <clchiou@gmail.com>2010-12-06 04:00:03 +0000
commitf9644867712c531427567ca4f936f507cd34f1b1 (patch)
treeaa4c1da71c4347c6a8eae61558a02c41e9812098 /lib/Target/PTX
parentf8803fe4177739f9a6900198f601808eb27934d9 (diff)
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ptx: add shift instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120982 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PTX')
-rw-r--r--lib/Target/PTX/PTXInstrInfo.td27
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/Target/PTX/PTXInstrInfo.td b/lib/Target/PTX/PTXInstrInfo.td
index 01e0f2a..ccd77df 100644
--- a/lib/Target/PTX/PTXInstrInfo.td
+++ b/lib/Target/PTX/PTXInstrInfo.td
@@ -46,6 +46,11 @@ def MEMii : Operand<i32> {
// PTX Specific Node Definitions
//===----------------------------------------------------------------------===//
+// PTX allow generic 3-reg shifts like shl r0, r1, r2
+def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
+def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
+def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
+
def PTXexit
: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
def PTXret
@@ -66,6 +71,22 @@ multiclass INT3<string opcstr, SDNode opnode> {
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
}
+// no %type directive, non-communtable
+multiclass INT3ntnc<string opcstr, SDNode opnode> {
+ def rr : InstPTX<(outs RRegs32:$d),
+ (ins RRegs32:$a, RRegs32:$b),
+ !strconcat(opcstr, "\t$d, $a, $b"),
+ [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
+ def ri : InstPTX<(outs RRegs32:$d),
+ (ins RRegs32:$a, i32imm:$b),
+ !strconcat(opcstr, "\t$d, $a, $b"),
+ [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
+ def ir : InstPTX<(outs RRegs32:$d),
+ (ins i32imm:$a, RRegs32:$b),
+ !strconcat(opcstr, "\t$d, $a, $b"),
+ [(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>;
+}
+
multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
def ri : InstPTX<(outs RC:$d),
(ins MEMri:$a),
@@ -86,6 +107,12 @@ multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
defm ADD : INT3<"add", add>;
defm SUB : INT3<"sub", sub>;
+///===- Logic and Shift Instructions --------------------------------------===//
+
+defm SHL : INT3ntnc<"shl.b32", PTXshl>;
+defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
+defm SRA : INT3ntnc<"shr.s32", PTXsra>;
+
///===- Data Movement and Conversion Instructions -------------------------===//
let neverHasSideEffects = 1 in {