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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-05-15 15:07:06 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-05-15 15:07:06 +0000
commit9122396a4dea52cf917062782fc2f39c7dc698bb (patch)
tree5a54ae3605d13a5a8617bce46e8ac69f5748943f /lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
parentddbf053a4cad58393a389f264c51923111eba3db (diff)
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[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp')
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index 3ee0bd5..b1ac4a6 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -57,13 +57,13 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case FK_Data_1:
return 1;
case FK_Data_2:
+ case PPC::fixup_ppc_ha16:
+ case PPC::fixup_ppc_lo16:
+ case PPC::fixup_ppc_lo16_ds:
return 2;
case FK_Data_4:
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_br24:
- case PPC::fixup_ppc_ha16:
- case PPC::fixup_ppc_lo16:
- case PPC::fixup_ppc_lo16_ds:
return 4;
case FK_Data_8:
return 8;
@@ -100,9 +100,9 @@ public:
// name offset bits flags
{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_lo16", 16, 16, 0 },
- { "fixup_ppc_ha16", 16, 16, 0 },
- { "fixup_ppc_lo16_ds", 16, 14, 0 },
+ { "fixup_ppc_lo16", 0, 16, 0 },
+ { "fixup_ppc_ha16", 0, 16, 0 },
+ { "fixup_ppc_lo16_ds", 0, 14, 0 },
{ "fixup_ppc_tlsreg", 0, 0, 0 },
{ "fixup_ppc_nofixup", 0, 0, 0 }
};