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| author | Bill Wendling <isanbard@gmail.com> | 2013-06-18 07:20:20 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-06-18 07:20:20 +0000 |
| commit | 99cb622041a0839c7dfcf0263c5102a305a0fdb5 (patch) | |
| tree | 7890d4314940f3ef004cd8c2877343f14620a69a /lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | |
| parent | c4e6b540f05932eea37ca10b6c1fded522777954 (diff) | |
| download | external_llvm-99cb622041a0839c7dfcf0263c5102a305a0fdb5.zip external_llvm-99cb622041a0839c7dfcf0263c5102a305a0fdb5.tar.gz external_llvm-99cb622041a0839c7dfcf0263c5102a305a0fdb5.tar.bz2 | |
Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 31c73ae..420c01b 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -191,7 +191,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, // Return the thread-pointer register's encoding. Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_tlsreg)); - return CTX.getRegisterInfo().getEncodingValue(PPC::X13); + return CTX.getRegisterInfo()->getEncodingValue(PPC::X13); } unsigned PPCMCCodeEmitter:: @@ -202,7 +202,7 @@ get_crbitm_encoding(const MCInst &MI, unsigned OpNo, MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MTCRF8) && (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); - return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg()); + return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); } @@ -214,7 +214,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, // The GPR operand should come through here though. assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); - return CTX.getRegisterInfo().getEncodingValue(MO.getReg()); + return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); } assert(MO.isImm() && |
