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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-05 12:22:36 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-05 12:22:36 +0000
commit23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df (patch)
tree93954d1ea2e8230d74fceb259dbc4566b6ea8901 /lib/Target/PowerPC/MCTargetDesc
parent87b8a7f9996ee7463b787fc85394287de903c7d7 (diff)
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[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc')
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp3
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp6
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h6
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp2
4 files changed, 6 insertions, 11 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index b37a179..4f999a1 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -30,7 +30,6 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
case FK_Data_2:
case FK_Data_4:
case FK_Data_8:
- case PPC::fixup_ppc_tlsreg:
case PPC::fixup_ppc_nofixup:
return Value;
case PPC::fixup_ppc_brcond14:
@@ -64,7 +63,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
return 4;
case FK_Data_8:
return 8;
- case PPC::fixup_ppc_tlsreg:
case PPC::fixup_ppc_nofixup:
return 0;
}
@@ -101,7 +99,6 @@ public:
{ "fixup_ppc_brcond14abs", 16, 14, 0 },
{ "fixup_ppc_half16", 0, 16, 0 },
{ "fixup_ppc_half16ds", 0, 14, 0 },
- { "fixup_ppc_tlsreg", 0, 0, 0 },
{ "fixup_ppc_nofixup", 0, 0, 0 }
};
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
index 76cf43f..ffc5002 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
@@ -289,9 +289,6 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
break;
}
break;
- case PPC::fixup_ppc_tlsreg:
- Type = ELF::R_PPC64_TLS;
- break;
case PPC::fixup_ppc_nofixup:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
@@ -301,6 +298,9 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
case MCSymbolRefExpr::VK_TLSLD:
Type = ELF::R_PPC64_TLSLD;
break;
+ case MCSymbolRefExpr::VK_PPC_TLS:
+ Type = ELF::R_PPC64_TLS;
+ break;
}
break;
case FK_Data_8:
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h b/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
index 0438c0e..68de8c1 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
@@ -41,11 +41,9 @@ enum Fixups {
/// implied 2 zero bits for instrs like 'std'.
fixup_ppc_half16ds,
- /// fixup_ppc_tlsreg - Insert thread-pointer register number.
- fixup_ppc_tlsreg,
-
/// fixup_ppc_nofixup - Not a true fixup, but ties a symbol to a call
- /// to __tls_get_addr for the TLS general and local dynamic models.
+ /// to __tls_get_addr for the TLS general and local dynamic models,
+ /// or inserts the thread-pointer register number.
fixup_ppc_nofixup,
// Marker
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 27ad980..59ba9c4 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -209,7 +209,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
// hint to the linker that this statement is part of a relocation sequence.
// Return the thread-pointer register's encoding.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_tlsreg));
+ (MCFixupKind)PPC::fixup_ppc_nofixup));
return CTX.getRegisterInfo()->getEncodingValue(PPC::X13);
}