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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-17 05:11:54 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-17 05:11:54 +0000 |
| commit | 9e36843964abce1e4f2db23b0b2c3ec8490fe601 (patch) | |
| tree | 66986dbc8e32cdbb19444834c1332ce5e360512a /lib/Target/PowerPC/Makefile | |
| parent | 8283ec7c1cb7ec34e5393c553df3edbaba671693 (diff) | |
| download | external_llvm-9e36843964abce1e4f2db23b0b2c3ec8490fe601.zip external_llvm-9e36843964abce1e4f2db23b0b2c3ec8490fe601.tar.gz external_llvm-9e36843964abce1e4f2db23b0b2c3ec8490fe601.tar.bz2 | |
Rewrite targets/rules to generate files for just PowerPC or PPC{32,64}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15862 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/Makefile')
| -rw-r--r-- | lib/Target/PowerPC/Makefile | 37 |
1 files changed, 18 insertions, 19 deletions
diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile index f210964..693b25d 100644 --- a/lib/Target/PowerPC/Makefile +++ b/lib/Target/PowerPC/Makefile @@ -13,39 +13,38 @@ include $(LEVEL)/Makefile.common TARGET = PowerPC # Make sure that tblgen is run, first thing. -$(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \ - PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \ - PowerPCGenInstrInfo.inc PowerPCGenCodeEmitter.inc \ - PowerPCGenAsmWriter.inc +$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \ + PowerPCGenCodeEmitter.inc PowerPCGenAsmWriter.inc \ + PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \ + PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc -TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ - $(SourceDir)/../Target.td +TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td -$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register names with tblgen" +%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN) + @echo "Building PowerPC register names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ -$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register information header with tblgen" +%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN) + @echo "Building `basename $<` register information header with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ -$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register information implementation with tblgen" +%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN) + @echo "Building `basename $<` register information implementation with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ -$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td instruction names with tblgen" +$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET) instruction names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ -$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td instruction information with tblgen" +%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET) instruction information with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ -$(TARGET)GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td code emitter" +$(TARGET)GenCodeEmitter.inc:: PPC32.td $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET) code emitter" $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@ -$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN) +$(TARGET)GenAsmWriter.inc:: PPC32.td $(TDFILES) $(TBLGEN) @echo "Building $(TARGET).td assembly writer with tblgen" $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@ |