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authorHal Finkel <hfinkel@anl.gov>2013-01-30 21:17:42 +0000
committerHal Finkel <hfinkel@anl.gov>2013-01-30 21:17:42 +0000
commit5bb16fdbb363abee2b9495116ff1a97568460cae (patch)
tree4fa301d922726dcc06b17c87ca00bb5165e9242b /lib/Target/PowerPC/PPC.td
parent2f89e8144b960468e4135f6d17cb6aac69197cbb (diff)
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Add definitions for the PPC a2q core marked as having QPX available
This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
-rw-r--r--lib/Target/PowerPC/PPC.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index cb15dad..d3bcbae 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -58,6 +58,8 @@ def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
"Enable the isel instruction">;
def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
"Enable Book E instructions">;
+def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
+ "Enable QPX instructions">;
//===----------------------------------------------------------------------===//
// Register File Description
@@ -109,6 +111,11 @@ def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
FeatureSTFIWX, FeatureISEL,
Feature64Bit
/*, Feature64BitRegs */]>;
+def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
+ FeatureMFOCRF, FeatureFSqrt,
+ FeatureSTFIWX, FeatureISEL,
+ Feature64Bit /*, Feature64BitRegs */,
+ FeatureQPX]>;
def : Processor<"pwr6", G5Itineraries,
[DirectivePwr6, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,