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| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-11 19:57:01 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-11 19:57:01 +0000 |
| commit | bd5cafd9bbba2180e7179436fb29071201d5ea9f (patch) | |
| tree | 8ad1aeeaebe4d0092e8f63ce3df61a7e0eb44a87 /lib/Target/PowerPC/PPC.td | |
| parent | 9770be91de745e4727c65c45d13de2a787aef89f (diff) | |
| download | external_llvm-bd5cafd9bbba2180e7179436fb29071201d5ea9f.zip external_llvm-bd5cafd9bbba2180e7179436fb29071201d5ea9f.tar.gz external_llvm-bd5cafd9bbba2180e7179436fb29071201d5ea9f.tar.bz2 | |
Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index fd08291..91e0717 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -44,8 +44,8 @@ def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", "Enable 64-bit registers usage for ppc32 [beta]">; def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", "Enable Altivec instructions">; -def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true", - "Enable GPUL instructions">; +def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", + "Enable the MFOCRF instruction">; def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", "Enable the fsqrt instruction">; def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", @@ -84,11 +84,11 @@ def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>; def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>; def : Processor<"970", G5Itineraries, [Directive970, FeatureAltivec, - FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"g5", G5Itineraries, [Directive970, FeatureAltivec, - FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, FeatureFSqrt, FeatureSTFIWX, @@ -96,16 +96,16 @@ def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, /*, Feature64BitRegs */]>; def : Processor<"pwr6", G5Itineraries, [DirectivePwr6, FeatureAltivec, - FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"pwr7", G5Itineraries, [DirectivePwr7, FeatureAltivec, - FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"ppc", G3Itineraries, [Directive32]>; def : Processor<"ppc64", G5Itineraries, [Directive64, FeatureAltivec, - FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; |