PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15851 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 59 insertions, 0 deletions

diff --git a/lib/Target/PowerPC/PPC64InstrInfo.cpp b/lib/Target/PowerPC/PPC64InstrInfo.cpp
new file mode 100644
index 0000000..3a68ad6
--- /dev/null
+++ b/lib/Target/PowerPC/PPC64InstrInfo.cpp
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+//===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the PowerPC implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PowerPC.h"
+#include "PPC64InstrInfo.h"
+#include "PPC64GenInstrInfo.inc"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include <iostream>
+using namespace llvm;
+
+PPC64InstrInfo::PPC64InstrInfo()
+  : TargetInstrInfo(PPC64Insts, sizeof(PPC64Insts)/sizeof(PPC64Insts[0])) { }
+
+bool PPC64InstrInfo::isMoveInstr(const MachineInstr& MI,
+                                 unsigned& sourceReg,
+                                 unsigned& destReg) const {
+  MachineOpCode oc = MI.getOpcode();
+  if (oc == PPC::OR) {                      // or r1, r2, r2
+    assert(MI.getNumOperands() == 3 &&
+           MI.getOperand(0).isRegister() &&
+           MI.getOperand(1).isRegister() &&
+           MI.getOperand(2).isRegister() &&
+           "invalid PPC OR instruction!");
+    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+    }
+  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
+    assert(MI.getNumOperands() == 3 &&
+           MI.getOperand(0).isRegister() &&
+           MI.getOperand(2).isImmediate() &&
+           "invalid PPC ADDI instruction!");
+    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+    }
+  } else if (oc == PPC::FMR) {              // fmr r1, r2
+    assert(MI.getNumOperands() == 2 &&
+           MI.getOperand(0).isRegister() &&
+           MI.getOperand(1).isRegister() &&
+           "invalid PPC FMR instruction");
+    sourceReg = MI.getOperand(1).getReg();
+    destReg = MI.getOperand(0).getReg();
+    return true;
+  }
+  return false;
+}