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| author | Nate Begeman <natebegeman@mac.com> | 2005-07-20 22:42:00 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-07-20 22:42:00 +0000 |
| commit | adeb43ddf4eac9e75b7c8e79fa832f72922a2926 (patch) | |
| tree | a348bba538834e4ae4789b1cf3512fdfad43733f /lib/Target/PowerPC/PPCCodeEmitter.cpp | |
| parent | a57743780954ee455896f917d73af91f3430f0b1 (diff) | |
| download | external_llvm-adeb43ddf4eac9e75b7c8e79fa832f72922a2926.zip external_llvm-adeb43ddf4eac9e75b7c8e79fa832f72922a2926.tar.gz external_llvm-adeb43ddf4eac9e75b7c8e79fa832f72922a2926.tar.bz2 | |
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCCodeEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index b957fe6..0b945ab 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -187,9 +187,9 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { if (MO.isRegister()) { rv = enumRegToMachineReg(MO.getReg()); - // Special encoding for MTCRF and MFCRF, which uses a bit mask for the + // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the // register, not the register number directly. - if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFCRF) && + if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) && (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) { rv = 0x80 >> rv; } |