Remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 28 insertions, 28 deletions

diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 574e21e..b957fe6 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -1,12 +1,12 @@
 //===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
 // JIT-compile bytecode to native PowerPC.
 //
@@ -42,7 +42,7 @@ namespace {
     int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
 
   public:
-    PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M) 
+    PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
       : TM(T), MCE(M) {}
 
     const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -58,7 +58,7 @@ namespace {
     /// emitWord - write a 32-bit word to memory at the current PC
     ///
     void emitWord(unsigned w) { MCE.emitWord(w); }
-    
+
     /// getValueBit - return the particular bit of Val
     ///
     unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
@@ -80,7 +80,7 @@ namespace {
 bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
                                                     MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC
-  PM.add(new PPC32CodeEmitter(*this, MCE)); 
+  PM.add(new PPC32CodeEmitter(*this, MCE));
   // Delete machine code for this function after emitting it
   PM.add(createMachineCodeDeleter());
   return false;
@@ -102,7 +102,7 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
                     << "\n");
     unsigned Instr = *Ref;
     intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
-    
+
     switch (Instr >> 26) {
     default: assert(0 && "Unknown branch user!");
     case 18:  // This is B or BL
@@ -142,36 +142,36 @@ void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
 
 static unsigned enumRegToMachineReg(unsigned enumReg) {
   switch (enumReg) {
-  case PPC::R0 :  case PPC::F0 :  case PPC::CR0:  return  0;  
-  case PPC::R1 :  case PPC::F1 :  case PPC::CR1:  return  1; 
+  case PPC::R0 :  case PPC::F0 :  case PPC::CR0:  return  0;
+  case PPC::R1 :  case PPC::F1 :  case PPC::CR1:  return  1;
   case PPC::R2 :  case PPC::F2 :  case PPC::CR2:  return  2;
-  case PPC::R3 :  case PPC::F3 :  case PPC::CR3:  return  3; 
-  case PPC::R4 :  case PPC::F4 :  case PPC::CR4:  return  4; 
+  case PPC::R3 :  case PPC::F3 :  case PPC::CR3:  return  3;
+  case PPC::R4 :  case PPC::F4 :  case PPC::CR4:  return  4;
   case PPC::R5 :  case PPC::F5 :  case PPC::CR5:  return  5;
-  case PPC::R6 :  case PPC::F6 :  case PPC::CR6:  return  6; 
-  case PPC::R7 :  case PPC::F7 :  case PPC::CR7:  return  7; 
+  case PPC::R6 :  case PPC::F6 :  case PPC::CR6:  return  6;
+  case PPC::R7 :  case PPC::F7 :  case PPC::CR7:  return  7;
   case PPC::R8 :  case PPC::F8 :  return  8;
-  case PPC::R9 :  case PPC::F9 :  return  9; 
-  case PPC::R10:  case PPC::F10:  return 10; 
+  case PPC::R9 :  case PPC::F9 :  return  9;
+  case PPC::R10:  case PPC::F10:  return 10;
   case PPC::R11:  case PPC::F11:  return 11;
-  case PPC::R12:  case PPC::F12:  return 12; 
-  case PPC::R13:  case PPC::F13:  return 13; 
+  case PPC::R12:  case PPC::F12:  return 12;
+  case PPC::R13:  case PPC::F13:  return 13;
   case PPC::R14:  case PPC::F14:  return 14;
-  case PPC::R15:  case PPC::F15:  return 15; 
-  case PPC::R16:  case PPC::F16:  return 16; 
+  case PPC::R15:  case PPC::F15:  return 15;
+  case PPC::R16:  case PPC::F16:  return 16;
   case PPC::R17:  case PPC::F17:  return 17;
-  case PPC::R18:  case PPC::F18:  return 18; 
-  case PPC::R19:  case PPC::F19:  return 19; 
+  case PPC::R18:  case PPC::F18:  return 18;
+  case PPC::R19:  case PPC::F19:  return 19;
   case PPC::R20:  case PPC::F20:  return 20;
   case PPC::R21:  case PPC::F21:  return 21;
-  case PPC::R22:  case PPC::F22:  return 22; 
-  case PPC::R23:  case PPC::F23:  return 23; 
+  case PPC::R22:  case PPC::F22:  return 22;
+  case PPC::R23:  case PPC::F23:  return 23;
   case PPC::R24:  case PPC::F24:  return 24;
-  case PPC::R25:  case PPC::F25:  return 25; 
-  case PPC::R26:  case PPC::F26:  return 26; 
+  case PPC::R25:  case PPC::F25:  return 25;
+  case PPC::R26:  case PPC::F26:  return 26;
   case PPC::R27:  case PPC::F27:  return 27;
-  case PPC::R28:  case PPC::F28:  return 28; 
-  case PPC::R29:  case PPC::F29:  return 29; 
+  case PPC::R28:  case PPC::F28:  return 28;
+  case PPC::R29:  case PPC::F29:  return 29;
   case PPC::R30:  case PPC::F30:  return 30;
   case PPC::R31:  case PPC::F31:  return 31;
   default:
@@ -181,7 +181,7 @@ static unsigned enumRegToMachineReg(unsigned enumReg) {
 }
 
 int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
-                                        
+
   int rv = 0; // Return value; defaults to 0 for unhandled cases
                   // or things that get fixed up later by the JIT.
   if (MO.isRegister()) {