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author | Michael Liao <michael.liao@intel.com> | 2013-03-01 18:40:30 +0000 |
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committer | Michael Liao <michael.liao@intel.com> | 2013-03-01 18:40:30 +0000 |
commit | a6b20ced765b67a85d9219d0c8547fc9c133e14f (patch) | |
tree | f3a6b8ebc9b5844b4eebe89f46f9dc3ba451b790 /lib/Target/PowerPC/PPCISelLowering.h | |
parent | b8f307b2d6b5fb1380803ff91696902bebbef7c6 (diff) | |
download | external_llvm-a6b20ced765b67a85d9219d0c8547fc9c133e14f.zip external_llvm-a6b20ced765b67a85d9219d0c8547fc9c133e14f.tar.gz external_llvm-a6b20ced765b67a85d9219d0c8547fc9c133e14f.tar.bz2 |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.h')
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index f5d418c..3931384 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -329,7 +329,7 @@ namespace llvm { /// DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; - virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } + virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } /// getSetCCResultType - Return the ISD::SETCC ValueType virtual EVT getSetCCResultType(EVT VT) const; |