Change codegen for setcc to read the bit directly out of the condition

  register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 181f2b3..e2cec77 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -392,13 +392,13 @@ class XFXForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
   let Inst{31}    = 0;
 }
 
-class XFXForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx, 
+class XFXForm_5<bits<6> opcode, bit mfcrf, bits<10> xo, bit ppc64, bit vmx, 
                 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
   bits<8>  FXM;
   bits<5>  ST;
    
   let Inst{6-10}  = ST;
-  let Inst{11}    = 0;
+  let Inst{11}    = mfcrf;
   let Inst{12-19} = FXM;
   let Inst{20}    = 0;
   let Inst{21-30} = xo;