Fix a minor bug (ORo didn't mark that it set CR0).

Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 6 deletions

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 108fd45..d933705 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -10,6 +10,14 @@
 //
 //===----------------------------------------------------------------------===//
 
+// DOT - This is a marker that should be added to instructions that set the
+// flags in CR0.
+class DOT {
+  list<Register> Defs = [CR0];
+  bit RC = 1;
+}
+
+
 class Format<bits<5> val> {
   bits<5> Value = val;
 }
@@ -217,18 +225,19 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
 // This is the same as XForm_base_r3xo, but the first two operands are swapped
 // when code is emitted.
 class XForm_base_r3xo_swapped
-        <bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+        <bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
          dag OL, string asmstr> 
   : I<opcode, ppc64, vmx, OL, asmstr> {
   bits<5> A;
   bits<5> RST;
   bits<5> B;
+  bit RC = 0;
 
   let Inst{6-10}  = RST;
   let Inst{11-15} = A;
   let Inst{16-20} = B;
   let Inst{21-30} = xo;
-  let Inst{31}    = rc;
+  let Inst{31}    = RC;
 }
 
 
@@ -243,9 +252,10 @@ class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
   let B = 0;
 }
 
-class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+class XForm_6<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
               dag OL, string asmstr> 
-  : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
+  : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
+}
 
 class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
               dag OL, string asmstr> 
@@ -253,13 +263,15 @@ class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
 
 class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
                dag OL, string asmstr> 
-  : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
+  : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
+  let RC = rc;
 }
 
 class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
                dag OL, string asmstr> 
-  : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
+  : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
   let B = 0;
+  let RC = rc;
 }
 
 class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,