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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2012-11-13 19:14:19 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2012-11-13 19:14:19 +0000 |
| commit | bc40df3f22a026ffce616cbd69ddb28148b82aad (patch) | |
| tree | 98b57dad400085732eb632e275717b4af6527892 /lib/Target/PowerPC/PPCInstrFormats.td | |
| parent | 2adc503f291d69763c5fc59a8e35d318ee22b77a (diff) | |
| download | external_llvm-bc40df3f22a026ffce616cbd69ddb28148b82aad.zip external_llvm-bc40df3f22a026ffce616cbd69ddb28148b82aad.tar.gz external_llvm-bc40df3f22a026ffce616cbd69ddb28148b82aad.tar.bz2 | |
Fix instruction encoding for "isel" on PowerPC,
using a new instruction format AForm_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrFormats.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index a41a027..2e83907 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -758,6 +758,26 @@ class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, let FRB = 0; } +class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { + bits<5> RT; + bits<5> RA; + bits<5> RB; + bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12). + bits<3> CR; + + let Pattern = pattern; + + let Inst{6-10} = RT; + let Inst{11-15} = RA; + let Inst{16-20} = RB; + let Inst{21-23} = CR; + let Inst{24-25} = BIBO{6-5}; + let Inst{26-30} = xo; + let Inst{31} = 0; +} + // 1.7.13 M-Form class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> |