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| author | Nowar Gu <nowar100@gmail.com> | 2011-07-01 23:28:45 +0800 |
|---|---|---|
| committer | Nowar Gu <nowar100@gmail.com> | 2011-07-01 23:37:27 +0800 |
| commit | 53d48080e55bf0c99cb7ca9de5b15a084d7324b5 (patch) | |
| tree | 98f4e257a61eebb14933d37ddc16678da0a7069d /lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | 039a79eb418211573bada57ec3a1edf5a9d6071e (diff) | |
| parent | ed5bc470aab7097c30e5f881158112f7830472f3 (diff) | |
| download | external_llvm-53d48080e55bf0c99cb7ca9de5b15a084d7324b5.zip external_llvm-53d48080e55bf0c99cb7ca9de5b15a084d7324b5.tar.gz external_llvm-53d48080e55bf0c99cb7ca9de5b15a084d7324b5.tar.bz2 | |
Merge upstream to r134237 at Fri. 1st July 2011.
Conflicts:
lib/Target/ARM/ARMCodeEmitter.cpp
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 53b0491..1ddc0f0 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -15,7 +15,6 @@ #include "PPCInstrBuilder.h" #include "PPCMachineFunctionInfo.h" #include "PPCPredicates.h" -#include "PPCGenInstrInfo.inc" #include "PPCTargetMachine.h" #include "PPCHazardRecognizers.h" #include "llvm/ADT/STLExtras.h" @@ -29,6 +28,9 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/MC/MCAsmInfo.h" +#define GET_INSTRINFO_MC_DESC +#include "PPCGenInstrInfo.inc" + namespace llvm { extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. @@ -37,8 +39,9 @@ extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. using namespace llvm; PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) - : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), - RI(*TM.getSubtargetImpl(), *this) {} + : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts), + PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), + TM(tm), RI(*TM.getSubtargetImpl(), *this) {} /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for /// this target when scheduling the DAG. @@ -120,7 +123,7 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { // destination register as well. if (Reg0 == Reg1) { // Must be two address instruction! - assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && + assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && "Expecting a two-address instruction!"); Reg2IsKill = false; ChangeReg0 = true; @@ -315,12 +318,12 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, else llvm_unreachable("Impossible reg-to-reg copy"); - const TargetInstrDesc &TID = get(Opc); - if (TID.getNumOperands() == 3) - BuildMI(MBB, I, DL, TID, DestReg) + const MCInstrDesc &MCID = get(Opc); + if (MCID.getNumOperands() == 3) + BuildMI(MBB, I, DL, MCID, DestReg) .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); else - BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); + BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); } bool |