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authorChris Lattner <sabre@nondot.org>2006-10-17 22:41:45 +0000
committerChris Lattner <sabre@nondot.org>2006-10-17 22:41:45 +0000
commitae1dc403274d3a64bcee31f15e2d25e4b7178811 (patch)
tree860399ca4d1a1c66586e537a403dc4e7718771a1 /lib/Target/PowerPC/PPCInstrInfo.h
parent72dc5852684bd56af68b3f344b295d9ff5c3a13f (diff)
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expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.h')
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index 265e1e7..dc16aed 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -77,6 +77,13 @@ public:
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
+ /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
+ /// instruction if it has one. This is used by codegen passes that update
+ /// DWARF line number info as they modify the code.
+ virtual unsigned getDWARF_LABELOpcode() const {
+ return PPC::DWARF_LABEL;
+ }
+
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//