diff options
author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-17 04:55:41 +0000 |
---|---|---|
committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-17 04:55:41 +0000 |
commit | f2ccb77ee9d8ab35866dae111fa36929689c7511 (patch) | |
tree | c1b71d510e6af6c32a71dd944bc85b6f468327b9 /lib/Target/PowerPC/PPCInstrInfo.h | |
parent | 2c38413b3f5420f45f2f8220b21862246d446dd0 (diff) | |
download | external_llvm-f2ccb77ee9d8ab35866dae111fa36929689c7511.zip external_llvm-f2ccb77ee9d8ab35866dae111fa36929689c7511.tar.gz external_llvm-f2ccb77ee9d8ab35866dae111fa36929689c7511.tar.bz2 |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.h')
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h new file mode 100644 index 0000000..17ef803 --- /dev/null +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -0,0 +1,56 @@ +//===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the PowerPC implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef POWERPC32_INSTRUCTIONINFO_H +#define POWERPC32_INSTRUCTIONINFO_H + +#include "PowerPCInstrInfo.h" +#include "PPC32RegisterInfo.h" + +namespace llvm { + +class PPC32InstrInfo : public TargetInstrInfo { + const PPC32RegisterInfo RI; +public: + PPC32InstrInfo(); + + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + /// + virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + + // + // Return true if the instruction is a register to register move and + // leave the source and dest operands in the passed parameters. + // + virtual bool isMoveInstr(const MachineInstr& MI, + unsigned& sourceReg, + unsigned& destReg) const; + + static unsigned invertPPCBranchOpcode(unsigned Opcode) { + switch (Opcode) { + default: assert(0 && "Unknown PPC branch opcode!"); + case PPC::BEQ: return PPC::BNE; + case PPC::BNE: return PPC::BEQ; + case PPC::BLT: return PPC::BGE; + case PPC::BGE: return PPC::BLT; + case PPC::BGT: return PPC::BLE; + case PPC::BLE: return PPC::BGT; + } + } +}; + +} + +#endif |