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| author | Owen Anderson <resistor@mac.com> | 2008-01-01 21:11:32 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2008-01-01 21:11:32 +0000 |
| commit | f6372aa1cc568df19da7c5023e83c75aa9404a07 (patch) | |
| tree | 9cc85598bdfe4e6af602fffcca57f03c61c0dc3f /lib/Target/PowerPC/PPCInstrInfo.h | |
| parent | 80fe5311b5e9e5c4642ff46ba2377173c17797f6 (diff) | |
| download | external_llvm-f6372aa1cc568df19da7c5023e83c75aa9404a07.zip external_llvm-f6372aa1cc568df19da7c5023e83c75aa9404a07.tar.gz external_llvm-f6372aa1cc568df19da7c5023e83c75aa9404a07.tar.bz2 | |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.h | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index ac3cf55..7591f77 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -103,11 +103,32 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) const; - void copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; + + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, int FrameIndex, + const TargetRegisterClass *RC) const; + + virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr*> &NewMIs) const; + + virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const; + + virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr*> &NewMIs) const; + virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; }; |