Add support for fmul node of type v4f32.

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 13 insertions, 0 deletions

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 3ea0920..1a30985 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -897,6 +897,16 @@ def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vsubfp $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
+def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vxor $vD, $vA, $vB", VecFP,
+                      []>;
+                      
+// VX-Form Pseudo Instructions
+
+def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
+                      "vxor $vD, $vD, $vD", VecFP,
+                      []>;
+
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Patterns
@@ -951,6 +961,9 @@ def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
           (ADDIS GPRC:$in, tconstpool:$g)>;
 
+def : Pat<(fmul VRRC:$vA, VRRC:$vB),
+          (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>; 
+
 // Fused multiply add and multiply sub for packed float.  These are represented
 // separately from the real instructions above, for operations that must have
 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)