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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 06:52:27 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 06:52:27 +0000 |
| commit | 240b7f3324da70937d4fe6d0bd7278ae82849114 (patch) | |
| tree | 27ddd1a75efe424f797908f9e7b76d3a48101f31 /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | 6375e1b87b089093fecdb09f609251e91d1c2c4f (diff) | |
| download | external_llvm-240b7f3324da70937d4fe6d0bd7278ae82849114.zip external_llvm-240b7f3324da70937d4fe6d0bd7278ae82849114.tar.gz external_llvm-240b7f3324da70937d4fe6d0bd7278ae82849114.tar.bz2 | |
Allocate r0 on PPC
The R0 register can now be allocated because instructions
that cannot use R0 as a GPR have been appropriately marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 0ebf1e8..b48305e 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -134,7 +134,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(PPC::FP); Reserved.set(PPC::FP8); - Reserved.set(PPC::R0); Reserved.set(PPC::R1); Reserved.set(PPC::LR); Reserved.set(PPC::LR8); @@ -150,7 +149,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { if (Subtarget.isPPC64()) { Reserved.set(PPC::R13); - Reserved.set(PPC::X0); Reserved.set(PPC::X1); Reserved.set(PPC::X13); |