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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-24 23:03:18 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-24 23:03:18 +0000 |
| commit | 33276d95ef4191663d8e6b972481f9faf37ce541 (patch) | |
| tree | 040375cd6aec3eee3ecbe38cf9f980afb7be5684 /lib/Target/PowerPC/PPCRegisterInfo.td | |
| parent | c21763fd993f37d02c7a495e96c3e8eb4c0b4015 (diff) | |
| download | external_llvm-33276d95ef4191663d8e6b972481f9faf37ce541.zip external_llvm-33276d95ef4191663d8e6b972481f9faf37ce541.tar.gz external_llvm-33276d95ef4191663d8e6b972481f9faf37ce541.tar.bz2 | |
Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 632ae19..ca0e95f 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -241,14 +241,18 @@ def sub_eq : SubRegIndex { let NumberHack = 3; } def sub_un : SubRegIndex { let NumberHack = 4; } } -def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>; -def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>; -def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>; -def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>; +def : SubRegSet<sub_lt, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>; +def : SubRegSet<sub_gt, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>; +def : SubRegSet<sub_eq, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>; +def : SubRegSet<sub_un, + [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], + [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>; // Link register def LR : SPR<8, "lr">, DwarfRegNum<[65]>; |