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author | Hal Finkel <hfinkel@anl.gov> | 2013-09-11 23:05:25 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2013-09-11 23:05:25 +0000 |
commit | b7fbc5baad87eb5cc143193e66139824993883d3 (patch) | |
tree | 3c7ffbac65580880568aac5fa070adcba8aa3386 /lib/Target/PowerPC/PPCSubtarget.cpp | |
parent | 6c32111544d437128660e3fdb8701ae747f4a37b (diff) | |
download | external_llvm-b7fbc5baad87eb5cc143193e66139824993883d3.zip external_llvm-b7fbc5baad87eb5cc143193e66139824993883d3.tar.gz external_llvm-b7fbc5baad87eb5cc143193e66139824993883d3.tar.bz2 |
Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores
For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190558 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCSubtarget.cpp')
-rw-r--r-- | lib/Target/PowerPC/PPCSubtarget.cpp | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index f975f55..ace37c1 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -15,6 +15,7 @@ #include "PPC.h" #include "PPCRegisterInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/GlobalValue.h" #include "llvm/IR/Function.h" @@ -186,3 +187,41 @@ bool PPCSubtarget::enablePostRAScheduler( return OptLevel >= CodeGenOpt::Default; } +// Embedded cores need aggressive scheduling. +static bool needsAggressiveScheduling(unsigned Directive) { + switch (Directive) { + default: return false; + case PPC::DIR_440: + case PPC::DIR_A2: + case PPC::DIR_E500mc: + case PPC::DIR_E5500: + return true; + } +} + +bool PPCSubtarget::enableMachineScheduler() const { + // Enable MI scheduling for the embedded cores. + // FIXME: Enable this for all cores (some additional modeling + // may be necessary). + return needsAggressiveScheduling(DarwinDirective); +} + +void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, + MachineInstr *begin, + MachineInstr *end, + unsigned NumRegionInstrs) const { + if (needsAggressiveScheduling(DarwinDirective)) { + Policy.OnlyTopDown = false; + Policy.OnlyBottomUp = false; + } + + // Spilling is generally expensive on all PPC cores, so always enable + // register-pressure tracking. + Policy.ShouldTrackPressure = true; +} + +bool PPCSubtarget::useAA() const { + // Use AA during code generation for the embedded cores. + return needsAggressiveScheduling(DarwinDirective); +} + |