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| author | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
| commit | a7a5854f1c3710f4bedf069be4771b81e449f2a3 (patch) | |
| tree | 438c2801d45b3995eed10e57be580d2d2797f172 /lib/Target/PowerPC/PPCSubtarget.h | |
| parent | 6557f186896b9a4f57ea354ee04e0c74c389e0e1 (diff) | |
| download | external_llvm-a7a5854f1c3710f4bedf069be4771b81e449f2a3.zip external_llvm-a7a5854f1c3710f4bedf069be4771b81e449f2a3.tar.gz external_llvm-a7a5854f1c3710f4bedf069be4771b81e449f2a3.tar.bz2 | |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCSubtarget.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCSubtarget.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h index c98291e..e898a04 100644 --- a/lib/Target/PowerPC/PPCSubtarget.h +++ b/lib/Target/PowerPC/PPCSubtarget.h @@ -33,8 +33,8 @@ protected: /// Used by the ISel to turn in optimizations for POWER4-derived architectures bool IsGigaProcessor; - bool Is64Bit; - bool Has64BitRegs; + bool Has64BitSupport; + bool Use64BitRegs; bool HasAltivec; bool HasFSQRT; bool HasSTFIWX; @@ -66,12 +66,12 @@ public: bool hasFSQRT() const { return HasFSQRT; } bool hasSTFIWX() const { return HasSTFIWX; } - bool has64BitRegs() const { return Has64BitRegs; } + bool use64BitRegs() const { return Use64BitRegs; } bool hasAltivec() const { return HasAltivec; } bool isAIX() const { return IsAIX; } bool isDarwin() const { return IsDarwin; } - bool is64Bit() const { return Is64Bit; } + bool has64BitSupport() const { return Has64BitSupport; } bool isGigaProcessor() const { return IsGigaProcessor; } }; } // End llvm namespace |