kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 14 insertions, 83 deletions

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index b781ca5..78dbaa6 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -535,75 +535,6 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
   return 0;
 }
 
-
-SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
-  SDNode *N = Op.Val;
-  SDOperand LHSL, LHSH;
-  Select(LHSL, N->getOperand(0));
-  Select(LHSH, N->getOperand(1));
-  
-  unsigned Imm;
-  bool ME = false, ZE = false;
-  if (isIntImmediate(N->getOperand(3), Imm)) {
-    ME = (signed)Imm == -1;
-    ZE = Imm == 0;
-  }
-  
-  std::vector<SDOperand> Result;
-  SDOperand Tmp;
-  SDNode *CarryFromLo;
-  if (isIntImmediate(N->getOperand(2), Imm) &&
-      ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
-    // Codegen the low 32 bits of the add.  Interestingly, there is no
-    // shifted form of add immediate carrying.
-    CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
-                                        LHSL, getI32Imm(Imm));
-  } else {
-    Select(Tmp, N->getOperand(2));
-    CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
-                                        LHSL, Tmp);
-  }
-  
-  // Codegen the high 32 bits, adding zero, minus one, or the full value
-  // along with the carry flag produced by addc/addic.
-  SDOperand ResultHi;
-  if (ZE)
-    ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH,
-                                               SDOperand(CarryFromLo, 1)), 0);
-  else if (ME)
-    ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH,
-                                               SDOperand(CarryFromLo, 1)), 0);
-  else {
-    Select(Tmp, N->getOperand(3));
-    ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
-                                            Tmp, SDOperand(CarryFromLo, 1)), 0);
-  }
-  Result.push_back(SDOperand(CarryFromLo, 0));
-  Result.push_back(ResultHi);
-  
-  CodeGenMap[Op.getValue(0)] = Result[0];
-  CodeGenMap[Op.getValue(1)] = Result[1];
-  return Result[Op.ResNo];
-}
-SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
-  SDNode *N = Op.Val;
-  SDOperand LHSL, LHSH, RHSL, RHSH;
-  Select(LHSL, N->getOperand(0));
-  Select(LHSH, N->getOperand(1));
-  Select(RHSL, N->getOperand(2));
-  Select(RHSH, N->getOperand(3));
-  
-  std::vector<SDOperand> Result;
-  Result.push_back(SDOperand(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32,
-                                                   MVT::Flag, RHSL, LHSL), 0));
-  Result.push_back(SDOperand(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32,
-                                                   RHSH, LHSH,
-                                                   Result[0].getValue(1)), 0));
-  CodeGenMap[Op.getValue(0)] = Result[0];
-  CodeGenMap[Op.getValue(1)] = Result[1];
-  return Result[Op.ResNo];
-}
-
 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
   SDNode *N = Op.Val;
   unsigned Imm;
@@ -846,12 +777,6 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   
   switch (N->getOpcode()) {
   default: break;
-  case ISD::ADD_PARTS:
-    Result = SelectADD_PARTS(Op);
-    return;
-  case ISD::SUB_PARTS:
-    Result = SelectSUB_PARTS(Op);
-    return;
   case ISD::SETCC:
     Result = SelectSETCC(Op);
     return;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 7c184ab..30f4e9b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -302,7 +302,7 @@ def ADDI   : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
 def ADDIC  : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "addic $rD, $rA, $imm", IntGeneral,
-                     []>;
+                     [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>;
 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "addic. $rD, $rA, $imm", IntGeneral,
                      []>;
@@ -684,10 +684,10 @@ def ADD8  : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
                      [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
 def ADDC  : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
                      "addc $rT, $rA, $rB", IntGeneral,
-                     []>;
+                     [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>;
 def ADDE  : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
                      "adde $rT, $rA, $rB", IntGeneral,
-                     []>;
+                     [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
 def DIVD  : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
                      "divd $rT, $rA, $rB", IntDivD,
                      [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
@@ -723,22 +723,25 @@ def SUBF  : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
                      [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
                      "subfc $rT, $rA, $rB", IntGeneral,
-                     []>;
+                     [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>;
 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
                      "subfe $rT, $rA, $rB", IntGeneral,
-                     []>;
+                     [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
 def ADDME  : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
                       "addme $rT, $rA", IntGeneral,
-                      []>;
+                      [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
 def ADDZE  : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
                       "addze $rT, $rA", IntGeneral,
-                      []>;
+                      [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
 def NEG    : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
                       "neg $rT, $rA", IntGeneral,
                       [(set GPRC:$rT, (ineg GPRC:$rA))]>;
+def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
+                      "subfme $rT, $rA", IntGeneral,
+                      [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
                       "subfze $rT, $rA", IntGeneral,
-                      []>;
+                      [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
 
 // A-Form instructions.  Most of the instructions executed in the FPU are of
 // this type.
@@ -983,6 +986,9 @@ def : Pat<(or GPRC:$in, imm:$imm),
 // XOR an arbitrary immediate.
 def : Pat<(xor GPRC:$in, imm:$imm),
           (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
+// SUBFIC
+def : Pat<(subc immSExt16:$imm, GPRC:$in),
+          (SUBFIC GPRC:$in, imm:$imm)>;
 
 // Return void support.
 def : Pat<(ret), (BLR)>;